Semiconductor device and manufacturing method thereof

ABSTRACT

A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.

BACKGROUND

Efforts have been made to enhance performance of an IGBT by carrying outmany improvements. Here, the performance of an IGBT is identified as aswitch that completely cuts off current while holding an applied voltagewhen turned-off, and allows current to flow with the least possiblevoltage drop, i.e., with the least possible on-resistance for the leastpossible power loss when turned-on. For purposes of an operation anIGBT, a collector is typically expressed as an “anode” and an emitter istypically expressed as a “cathode.”

There exists a tradeoff relationship between the maximum voltage thatcan be held by an IGBT, i.e., a magnitude of a breakdown voltage, and avoltage drop when the IGBT is turned-on, where an IGBT with a higherbreakdown voltage has a higher on-voltage. Ultimately, the limit of theoptimum value in the tradeoff relation is determined by physicalproperties of silicon. For enhancing the optimum value in the tradeoff,property/structural changes are needed to prevent a local electric fieldconcentration buildup when an IGBT holds an applied voltage.

Another important measure representing performance of an IGBT is atradeoff between an on-voltage and a switching loss (in particular, aturn-off loss). An IGBT, being a switching device, carries out anoperation from being turned-on to being turned-off, or from beingturned-off to being turned-on. At an instant of such a switchingoperation, a large loss is produced per unit time. In general, an IGBTwith a lower on-voltage is turned-off more slowly and produces a largerturn-off loss. Making the turn-off loss smaller causes the on-voltage tobecome high. This is referred to as a relation that necessitates atradeoff. By improving such a tradeoff, performance of an IGBT can beenhanced. Note that a turn-on loss of an IGBT has a little dependence onthe on-voltage, but rather largely depends on the characteristics of thefree-wheeling diode used in combination with the IGBT.

For optimizing the tradeoff between the on-voltage and the turn-offloss, it is effective to optimize a distribution of excessive carriersin an IGBT in a turned-on state. For lowering the on-voltage, the amountof excessive carriers can be increased to lower the resistance value ofa drift layer. At the turning-off state, however, all of the excessivecarriers must be swept out from the device or made to disappear by anelectron-hole recombination. A large amount of excessive carriersincreases the turn-off loss. Therefore, for optimizing such a tradeoff,it is necessary to minimize the distribution of excessive carriers thatcauses the turn-off loss by the same lowered on-voltage.

For achieve the optimum tradeoff, it is necessary to lower the carrierconcentration on the anode side while increasing the carrierconcentration on the cathode side to thereby provide a ratio of thecarrier concentration on the anode side to the carrier concentration onthe cathode side to about 1:5. Furthermore, it is also necessary to holdthe carrier lifetime in the drift layer longest possible so that anaveraged carrier concentration in the drift layer becomes high.

When an IGBT is turned-off, the depletion layer expands from the p-njunction on the cathode side to the inside of the drift layer withprogress toward the anode layer on the bottom surface. At this time, ofexcessive carriers in the drift layer, holes are drawn out by anelectric field from the end of the depletion layer. This creates anelectron excessive state, where the excess of electrons are injectedinto the anode layer in a p-type through a neutral region. Thus, the p-njunction on the anode side is slightly forward-biased, which causesreverse injection of holes with the amount depending on the amount ofthe injected electrons. The holes brought by the reverse injection mergewith holes drawn out by the above-explained electric field and enter thedepletion layer.

Carriers (here, holes) carrying electric charges pass through the regionof the electric field toward the cathode side. Thus, work is to be donein the electric field on the carriers. The work done on the carriers inthe electric field eventually causes lattice vibration of crystallattices, such as those of silicon, due to collisions of carriers withthe crystal lattices, and is dissipated as heat. The dissipated energybecomes the turn-off loss. Note that the energy dissipated due to thecarriers drawn out before the depletion layer has extended out issmaller than the energy dissipated due to the carriers being drawn outwhen the depletion layer has extended out. This is because the depletionlayer before having extended out provides a small potential differencewhen the carriers pass through the depletion layer, by which small workis done in the depletion layer on the carriers in the electric field.

The above explanation is made from the microscopic viewpoint. From themacroscopic view point of the terminal voltage of a device, it meansthat current flowing before the anode-cathode voltage has finishedrising, i.e., flowing while the anode-cathode voltage is rising, makes asmaller contribution to the loss expressed by the product of the voltageand the current (voltage×current) than the current flowing after theanode-cathode voltage has finished rising. From the foregoing, it isknown that a carrier distribution deviating to the cathode side by thelater-described IE effect causes a smaller turn-off loss than thecarrier distribution deviating to the anode side under conditions that afraction of carriers drawn out under a low voltage is larger andon-voltages to both the distributions are the same.

The carrier concentration on the anode side can be reduced by reducingthe total amounts of impurity concentrations in the anode layer. This isnot so difficult in itself. However, in an IGBT with a low ratedbreakdown voltage, such as 600V, for reducing the total amounts ofimpurity concentrations in the anode layer, the thickness of the wafermust be brought to on the order of 100 μm or below. Because such a thinwafer must be handled during the manufacturing process, themanufacturing technique becomes complicated and difficult. Also, thecarrier concentration on the cathode side is increased due to the IEeffect.

For a cathode structure with a large IE effect, a structure such as theHiGT structure is proposed in which an n-layer with a high impurityconcentration is inserted in a cathode so as to surround a p-base of aplanar structure (see JP-A-2003-347549 and JP-T-2002-532885, forexample). Moreover, in a trench gate structure, structures such as aCSTBT structure, in which an n-layer having a higher impurityconcentration than a drift layer is inserted in a mesa section betweenthe adjacent trenches, and an IEGT (Injection Enhancement GateTransistor) structure (see JP-A-8-316479, and Omura, et al, “Carrierinjection enhancement effect of high voltage MOS devices -Device physicsand design concept-”, ISPSD '97, pp. 217-220, for example), have beenproposed. In general, the IE effect in the trench structure is largerthan that in the planar structure.

The IE effect is discussed and reported in Udrea, et al, “A unifiedanalytical model for the carrier dynamics in Trench Insulated GateBipolar Transistor (TIGBT),” ISPSD '95, pp. 190-195, for example. Anoften drawn equivalent circuit of an IGBT is a combination of a MOSFET(Insulated Gate Field Effect Transistor having a Metal-Oxide-Semiconductor structure) and a bipolar transistor. However, with anactual device operation taken into consideration, the equivalent circuitcan be regarded, as an equivalent circuit shown in present FIG. 13,which is a combination of a MOSFET 51, a p-n-p bipolar transistor 52,and a p-i-n diode 53 (also disclosed in a co-pending application(attorney docket no FUJI:348) filed concurrently herewith).

FIG. 14 schematically illustrates a cross sectional view showing anarrangement of a principal part of a planar IGBT In FIG. 14, the rightregion 54 identified in dashed lines denotes a p-n-p bipolar transistorregion (hereinafter referred to as a p-n-p BJT region) and the leftregion 55 identified in dashed lines denotes a p-i-n diode region.Moreover, in FIG. 14, the arrows in solid lines represent flow ofelectron current, while the arrows in dotted lines represent flow ofhole current. In the present disclosure, the leading character “n” or“p” preceding the names of the layers and regions means that themajority carriers in the layers and the regions are electrons or holes,respectively. Moreover, a region (including a layer) named with aleading character “n⁺” or “p⁺” means that the region (including thelayer) has a higher impurity concentration than the region (includingthe layer) named with the leading character “n” or “p” without the sign“⁺”, respectively. Furthermore, a region (including a layer) named witha leading character “n⁺⁺” means that the region (including the layer)has a higher impurity concentration than the region (including thelayer) named with the leading character “n⁺”.

As shown in FIG. 14, electrons flow from an n⁺⁺-region 56 on the surfaceof a MOS section to a p-anode layer 61 on the bottom surface through ann⁺-inversion layer 58 on a p-layer 57 surrounding the n⁺⁺-region 56 andan n⁺-electron accumulation layer 60 on the surface of an n⁻-drift layer59. Part of the electron current becomes a base current of the p-n-p BJTregion 54. In the p-n-p BJT region 54, holes coming from the p-anodelayer 61 by diffusion or drift are only collected in the p-layer 57, andthe p-n junction between the p-layer 57 and the n⁻-drift layer 59 isslightly reverse-biased. Therefore, the concentration of minoritycarriers, i.e., holes in the n⁻-drift layer 59 near the p-n junction isextremely low.

The n-cathode in the p-i-n diode region 55 is the n⁺-electronaccumulation layer 60 on the surface of the n⁻-drift layer 59. Since thejunction between the n⁺-electron accumulation layer 60 and the n⁻-driftlayer 59 (hereinafter abbreviated as the n⁺/n⁻ junction) is slightlyforward-biased, electrons are injected into the n⁻-drift layer 59. Whenlarge current flows, an electron concentration becomes far higher thanthe doping concentration in the n⁻-drift layer 59 (a high-injectionstate). Moreover, for satisfying the charge neutrality condition, thereexist holes with the same concentration as that of electrons. Therefore,the concentration of minority carriers, i.e., holes, in the n⁻-driftlayer 59 near the n⁺/n⁻ junction is extremely high.

For achieving the optimum carrier distribution with a deviation to thecathode side in an IGBT, it is important to reduce the p-n-p BJT region54 and to increase a p-i-n diode region 55. Moreover, it is veryimportant to increase the amount of forward bias across the n⁺/n⁻junction to enhance electron injection. In every previously proposedstructure having the IE effect, proportion of the p-i-n diode region isincreased while attaining an increase in an amount of forward biasacross the n⁺/n⁻ junction.

Note that in an IGBT with a planar structure, reduction in proportion ofa region occupied by a p-base in a cell pitch reduces an on-voltage. Thereason for this is due to the increase in the proportion of the p-i-ndiode region with an additional rise in a lateral current density nearthe surface that caused an increase in a voltage drop, which enhancesthe effect of increasing the forward bias across the n⁺/n⁻ junction.From a different view point, the reason for increasing the forward biasacross the n⁺/n⁻ junction can be also said that the electric potentialof the n⁺-layer, having low resistance, is equal to the cathode electricpotential, while the electric potential of the n⁻-layer, having highresistance, is raised by the voltage drop due to the large current.

In the same way, in an IGBT with a trench structure, by reducingproportion of the p-n-p BJT region, the IE effect can be enhanced.Reduction in proportion of the p-n-p BJT region can be made by bringingthe p-base region to a floating state in a mesa section, for example.Moreover, the IE effect can be also enhanced by making the trench deeperto isolate the bottom of the trench from the p-n junction. Furthermore,by narrowing the width of the mesa section, the IE effect also can beenhanced. This, in both cases, is considered to be due to the increasein the hole current flowing in the mesa section that increases theforward bias across the n⁺/n⁻ junction due to a voltage drop.

Here, letting Nd be the doping concentration in the drift layer and Vnbe the forward bias applied across the n⁺/n⁻ junction, the electrondensity n on the n⁻-layer side of the n⁺/n⁻ junction can be expressed bythe following expression, where k is Boltzmann constant and T is anabsolute temperature:n=Nd*exp(Vn/kT).

As is apparent from the above expression, depending on the forward biasapplied to the n⁺/n⁻ junction, the electron density on the cathode sideis exponentially increased. To increase the amount of the forward bias,a voltage drop caused by a large current can be used. Moreover, as aredescribed in JP-A-2003-347549, JP-T-2002-532885 and JP-A-8-316479, theamount of the forward bias can be increased by also increasing then-type impurity concentration in the n⁺-layer. However, the HiGTstructure described in JP-A-2003-347549, being a planar structure,causes a large reduction in the forward breakdown voltage when then-type impurity concentration in the n⁺ buffer layer on the surface sideis excessively high.

In the CSTBT structure described in JP-A-8-316479, the n⁺-buffer layeron the surface side is held between the trench gate oxide films with itselectric potential continuing to the electric potential of thepolysilicon through the gate oxide film. This depletes the n⁺-bufferlayer on the surface side not only from the p-n junction but also fromthe boundaries of the trench gate oxide films on both sides. Thus, then⁺-buffer layer on the surface side is completely depleted with a lowforward bias. Therefore, although the n⁺-buffer layer on the surfaceside has a high impurity concentration, the electric field strengthinside the layer is reduced. Even though the forward bias is furtherincreased, the reduced electric field strength in the mesa sectionbetween the trenches hardly makes a local peak in the electric field.

This holds true to the principle of the MOSFET with a superjunctionstructure that includes in a drift section, instead of including a driftlayer formed with a uniform layer of a single conductivity type, aparallel p-n structure in which vertical-layer-like n-type regions, eachwith an increased impurity concentration, and vertical-layer-like p-typeregions are alternately joined. Thus, the CSTBT structure has suchcharacteristics that enhance the IE effect and yet make it hard to lowerthe forward breakdown voltage. The n⁺-buffer layer on the surface sidecauses, between the n⁻-drift layer, a diffusion potential that becomes apotential barrier for holes. Thus, the hole concentration in the driftlayer is increased (the first explanation).

As another explanation (the second explanation) for the reason, it canbe said that the n⁺-buffer layer on the surface side and the n⁻-driftlayer being forward-biased causes electrons to be injected from then⁺-buffer layer. Namely, in the n⁺/n⁻ junction, the n⁺-layer with a highimpurity concentration increases the electron injection efficiency,which increases the fraction of an electron current injected into then⁻-layer to hole current flowing in the n⁺-layer. For allowing holes toflow in the n⁺-layer by diffusion as minority carriers, the n⁺/n⁻junction must be forward-biased. Since the higher the impurityconcentration in the n⁺-layer is, the smaller the concentration of holesas minority carriers in a thermal equilibrium state becomes, a higheramount of a forward bias becomes necessary for still allowing the sameamount of hole current to flow with the impurity concentration in then⁺-layer made higher. Since a higher forward voltage increases anelectron current flowing into the n⁻-layer, an electron concentration isincreased. The second explanation expresses the previous firstexplanation physically in different words. As explained above, it isknown that, even in a related IGBT, such an element structure thatdeviates the carrier distribution to the cathode side due to the IEeffect, is preferably provided for optimizing the on-voltage to turn-offloss tradeoff.

However, the above-explained optimization of the on-voltage to turn-offloss tradeoff cannot always be said to be sufficient. It is consideredthat the carrier density on the cathode side in the on-state must befurther increased. Namely, it is not considered yet that the IE effectis sufficiently exhibited in such a MOS gate semiconductor device as arelated IGBT, for example. For example, even in a device to which atrench gate structure is adopted as in the above-explained CSTBTstructure or IEGT structure, although the tradeoff characteristic isimproved better than that in a previous device, there are stillpossibilities for improvement by further miniaturization.

Meanwhile, the manufacturing process of a semiconductor device with thetrench gate structure, although the manufactured trench gate structureexhibits a certain effect of improving the tradeoff as explained above,is longer and more complicated as compared with the manufacturingprocess of a semiconductor device with the planar structure. Thus, therate of acceptable products of a semiconductor device with the trenchgate structure is lower than the rate of acceptable products of asemiconductor device with the planar structure, which is liable toincrease the product cost of the semiconductor device with the trenchgate structure relatively higher than that of the semiconductor devicewith the planer structure.

In addition, further miniaturization of the semiconductor device withthe trench gate structure regardless of the enhancing characteristics ofthe semiconductor device will result in a higher manufacturing cost.Therefore, even though the miniaturization is not carried out to theultimate end, or even with a MOS gate semiconductor device without thetrench gate structure, to improve the above-explained tradeoff ispreferable from the view point of the rate of acceptable products andthe view point of the product cost. In the semiconductor device with thetrench gate structure, an electric field concentration is liable tooccur particularly at the bottom of the trench, to easily cause abreakdown in dielectric strength or avalanche breakdown, which is liableto degrade the on-voltage to breakdown voltage tradeoff. Moreover, thestructure has a problem in that, when the electric potential of the gateis made negative to that of the cathode, the electric field strength atthe bottom of the trench increases to further degrade the breakdownvoltage.

Accordingly, there remains a need to solve the above problems andprovide a semiconductor device and a method of manufacturing the devicewith further improved performance, namely providing a semiconductordevice capable of further improving the tradeoff between the on-voltageand the turn-off loss. The present invention addresses this need.

SUMMARY OF THE INVENTION

The present invention relates to a semiconductor device and amanufacturing method thereof, and particularly to a power semiconductordevice forming an IGBT (Insulated Gate Bipolar Transistor) and amanufacturing method thereof.

One aspect of the present invention is a semiconductor device having aMOS gate side surface structure. The device can include a semiconductorsubstrate of one conductivity type, a trench, a polycrystallinesemiconductor gate electrode region, a substrate insulator film, a gateinsulator film, a deposited semiconductor layer, an interlayer insulatorfilm, and an emitter electrode.

The trench is selectively formed into the semiconductor substrate. Thetrench can have a side wall forming an angle of 900 or less with thesurface of the semiconductor substrate.

The polycrystalline semiconductor gate electrode region fills thetrench. The substrate insulator film is positioned between the trenchand the polycrystalline semiconductor gate electrode region. The gateinsulator film covers the surface of the polycrystalline semiconductorgate electrode region.

The deposited semiconductor layer is in contact with the gate insulatorfilm in a region on the trench and in contact with the surface of thesemiconductor substrate in a region other than the region on the trench.The deposited semiconductor layer has a buffer region of the oneconductivity type in contact with the surface of the semiconductorsubstrate, a base region of the other conductivity type adjacent to thebuffer region on the gate insulator film, and an emitter region of theone conductivity type adjacent to the base region on the gate insulatorfilm on the side opposite to the buffer region.

The interlayer insulator film covers the buffer region. The emitterelectrode covers the interlayer insulator film and is in contact withboth the base region and the emitter region on the side opposite to theside in contact with the gate insulator film.

In an alternative embodiment, the semiconductor device can include asemiconductor substrate of one conductivity type, a substrate insulatorfilm, a deposited semiconductor layer, a gate electrode, a gateinsulator film, an interlayer insulator film, and an emitter electrode.

The substrate insulator film is selectively formed on the surface of thesemiconductor substrate, and the deposited semiconductor layer formed onthe surface of the semiconductor substrate and the substrate insulatorfilm. The deposited semiconductor layer has a buffer region of the oneconductivity type in contact with the surface of the semiconductorsubstrate, a base region of the other conductivity type adjacent to thebuffer region on the substrate insulator film, and an emitter region ofthe one conductivity type in the base region. The emitter region is at aposition holding the surface of the base region between the bufferregion and the emitter region.

The gate electrode can be of polycrystalline semiconductor on thesurface of the buffer region and on the surface of the base region heldbetween the buffer region and the emitter region. The gate insulatorfilm can be held between the gate electrode and the buffer region, andbetween the gate electrode and the base region. The interlayer insulatorfilm can cover the gate electrode of the polycrystalline semiconductor,and the emitter electrode can be in contact with both the base regionand the emitter region.

In the above embodiments, the buffer region can have an impurityconcentration higher than that of the semiconductor substrate, and thedeposited semiconductor layer can be a single or polycrystallinesemiconductor layer of the one conductivity type.

Another aspect of the present invention is a method of manufacturing thesemiconductor having the trench set forth above, the method can includeforming a masking insulator film on the surface of the semiconductorsubstrate, forming the trench in the semiconductor substrate using themasking insulator film as a mask, forming the substrate insulator filmon the surface of the semiconductor substrate, including the trench,depositing a polycrystalline semiconductor layer to a thickness morethan the depth of the trench, smoothing the surface of thepolycrystalline semiconductor layer by grinding the surface of thepolycrystalline semiconductor layer until the surface of the maskinginsulator film or the substrate insulator film becomes exposed, formingthe gate insulator film on the surface of the semiconductor substrate,removing all of the insulator films layered at the position of themasking insulator film to expose the surface of the semiconductorsubstrate, depositing a semiconductor layer of the one conductivity typeon the exposed semiconductor substrate and the gate insulator film sothat the semiconductor layer contacts the surface of the exposedsemiconductor substrate, forming the base region of the otherconductivity type and the emitter region of the one conductivity type inthe deposited semiconductor layer, the base region being formed adjacentto a region of the deposited semiconductor layer in contact with thesemiconductor substrate, the region being provided as a buffer region ofthe one conductivity type, and the emitter region being formed adjacentto the base region on the side opposite to the buffer region, andforming the emitter electrode covering the buffer region with aninterlayer insulator film between and in contact with both the baseregion of the other conductivity type and the emitter region.

Alternatively, the method of manufacturing the semiconductor device caninclude forming the substrate insulator film selectively covering thesurface of the semiconductor substrate of one conductivity type,depositing the polycrystalline semiconductor layer, removing part of thepolycrystalline semiconductor layer in contact with the surface of thesemiconductor substrate, forming the gate insulator film, exposing thesurface of the semiconductor substrate by removing part of the gateinsulator film in contact with the surface of the semiconductorsubstrate, depositing the semiconductor layer of the one conductivitytype on the exposed surface of the semiconductor substrate, forming inthe semiconductor layer the base region of the other conductivity typeadjacent to a buffer region of the one conductivity type as a region ofthe semiconductor layer in contact with the semiconductor substrate, andthe emitter region of the one conductivity type adjacent to the baseregion on the side opposite to the buffer region, and forming theemitter electrode covering the buffer region with an interlayerinsulator film between and in contact with both the base region and theemitter region.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A schematically illustrates a cross sectional view showing aprincipal part of a semiconductor substrate at the manufacturing step atwhich a masking oxide film is formed on a silicon substrate in onemanufacturing method of an IGBT according to the present invention.

FIG. 1B schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 1A at which a trench is formed in thesubstrate.

FIG. 1C schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 1B at which a substrate oxide film isformed on the inner surface of the trench.

FIG. 1D schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 1C at which a polysilicon layer isdeposited to fill the trench.

FIG. 2A schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 1D at which the surface of thepolysilicon layer is polished to be flat.

FIG. 2B schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 2A at which a gate oxide film is formedon the surface of the masking oxide film and the polysilicon layer.

FIG. 2C schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 2B at which oxide films are partlyremoved to expose the silicon substrate.

FIG. 2D schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 2C at which a doped polysilicon layer isformed on the substrate.

FIG. 3A schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 2D at which a source region, a baseregion, and a buffer region are formed in the doped polysilicon layer.

FIG. 3B schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 3A at which a BPSG film as an interlayerinsulator film is deposited and a contact hole is provided therein.

FIG. 3C schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 3B at which an emitter electrode isformed to form a surface structure on the MOS gate side of an IGBT

FIG. 4A schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepat which a masking oxide film is formed on a silicon substrate inanother manufacturing method of an IGBT according to the presentinvention.

FIG. 4B schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 4A at which a trench with a side wallangle smaller than 900 is formed in the substrate.

FIG. 4C schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 4B at which a substrate oxide film isformed on the inner surface of the trench.

FIG. 4D schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 4C at which a polysilicon layer isdeposited to fill the trench.

FIG. 5A schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 4D at which the surface of thepolysilicon layer is polished to be flat.

FIG. 5B schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 5A at which a gate oxide film is formedon the surface of the masking oxide film and the polysilicon layer.

FIG. 5C schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 5B at which oxide films are partlyremoved to expose the silicon substrate.

FIG. 5D schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 5C at which a doped polysilicon layer isformed on the substrate.

FIG. 6A schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 5D at which a source region, a baseregion, and a buffer region are formed in the doped polysilicon layer.

FIG. 6B schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 6A at which a BPSG film as an interlayerinsulator film is deposited and a contact hole is provided therein.

FIG. 6C schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 6B at which an emitter electrode isformed to form a surface structure on the MOS gate side of an IGBT

FIG. 7A schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepat which an oxide film is formed on a silicon substrate in yet anothermanufacturing method of an IGBT according to the present invention.

FIG. 7B schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 7A at which an opening is provided in theoxide film.

FIG. 7C schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 7B at which a substrate oxide film isformed on the substrate to have an opening provided at the center.

FIG. 7D schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 7C at which a silicon epitaxial layer ismade grown from the substrate to cover the entire surface.

FIG. 8A schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 7D at which the surface of the siliconepitaxial layer is polished to be flat.

FIG. 8B schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 8A at which a gate oxide film is formedover the entire surface.

FIG. 8C schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 8B at which a polysilicon layer to be agate electrode is formed on the entire surface.

FIG. 8D schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 8C at which the polysilicon layer ispartially removed to form a p-channel region and an n⁺⁺-source region inthe silicon epitaxial layer.

FIG. 9A schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 8D at which a BPSG film as an interlayerinsulator film is formed on the entire surface and an opening isprovided therein for contact.

FIG. 9B schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 9A at which an aluminum electrode isformed to form an IGBT by the method.

FIG. 10A schematically illustrates a cross sectional view showing aprincipal part of a semiconductor substrate at the manufacturing step atwhich a substrate oxide film is formed on a silicon substrate in yetanother manufacturing method of an IGBT according to the presentinvention.

FIG. 10B schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 10A at which on the substrate oxide filma polysilicon layer is deposited and an opening is provided therein.

FIG. 10C schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 10B at which a gate oxide film is formedon the polysilicon layer and the oxide film on a section withoutpolysilicon layer is removed to partially expose the silicon substrate.

FIG. 10D schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 10C at which a nitride film is formedover the entire surface before being etched into a stripe-like form withits end being left.

FIG. 11A schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 10D at which a silicon epitaxial layer ismade grown from the substrate to cover the entire surface.

FIG. 11B schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 11A at which the surface of the siliconepitaxial layer is polished to be flat.

FIG. 11C schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 11B at which a p-channel region and ann⁺⁺-source region are formed in the silicon epitaxial layer.

FIG. 11D schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 11C at which a BPSG film as an interlayerinsulator film is deposited on the entire surface and a contact hole isprovided therein.

FIG. 12 schematically illustrates a cross sectional view showing theprincipal part of the semiconductor substrate at the manufacturing stepnext to the step shown in FIG. 11D at which an aluminum electrode isformed to form a surface structure on the MOS gate side of an IGBT

FIG. 13 is a diagram showing an equivalent circuit of an IGBT

FIG. 14 schematically illustrates a cross sectional view showing anarrangement of a principal part of a planar IGBT

DETAILED DESCRIPTION

Detailed explanations of the present semiconductor device and method ofmanufacturing thereof is made with respect to specific examples. Thepresent invention, however, is not to be limited to these specificexamples.

FIG. 1A to FIG. 3C illustrate cross sectional views each showing aprincipal part of a semiconductor substrate at each of mainmanufacturing steps of one manufacturing method of a first embodiment ofan IGBT with a surface cathode side high injection structure. As shownin FIG. 1A, on a mirror-polished surface of an n-type FZ-siliconsubstrate 1, an oxide film 2 is selectively formed. The resistivity ofthe substrate is preferably within a range of the order of 30 to 200Ωcm, which is selected depending of the breakdown voltage of the IGBTFor example, manufacture by using a substrate with a resistivity of 80Ωcm allows an IGBT with a breakdown voltage of 1200V to be provided. Inthe method of forming the selective oxide film 2, an oxide film is firstformed on the entire surface of the silicon substrate 1 by thermaldiffusion or CVD growth, specified patterning is then carried out on thefilm and the patterned oxide film is selectively subjected to dryetching. The thickness of the oxide film 2 (hereinafter, whendistinction from other oxide films is necessary, referred to as themasking oxide film), can be one that is sufficiently resistant tosubsequent trench etching and to further subsequent chemical mechanicalpolishing (hereinafter abbreviated as CMP). The thickness is preferablywithin a range of the order of 0.1 to 0.8 μm. In the present example,the film thickness of the masking oxide film 2 was taken as 0.3 μm.

Next, as shown in FIG. 1B, a trench 3 is formed with the selective oxidefilm 2 used as a mask. The depth of the trench 3 is desirably within arange of 0.3 to 1 μm. In the example, the depth of the trench 3 wasdetermined as 0.7 μm. The width left between the trenches 3 and the cellpitch are preferably within the range of 1 to 5 μm and the range of 5 to20 μm, respectively. In the first example, the width left between thetrenches 3 and the cell pitch are taken as 3 μm and 10 μm, respectively.Thus, the width of the trench 3 becomes 7 μm. The side wall angle of theformed trench 3 (the angle formed by the surface of the substrate andthe side wall) is 90° in this example. The method of forming the trench3 is given as anisotropic dry etching using plasma RIE (Reactive IonEtching) of an ICP (Inductively Coupled Plasma) system. In the example1, the conditions for the etching were given as: the flow rate of SF₆=40sccm, the flow rate of HBr=40 sccm, the flow rate of O₂=60 sccm, thepressure=3.3 Pa, the plasma source power=400W, the bias power=100W andthe etching time=20 sec. However, the etching condition is not limitedto the above on condition that the desired cross sectional shape isobtained.

Subsequently, as shown in FIG. 1C and FIG. 1D, a thermal oxide film(hereinafter to be referred to as a substrate oxide film whendistinction from other oxide films is necessary) 4 is formed on theinner surface of the trench 3 by carrying out thermal oxidation, and apolysilicon layer 5 is thereafter deposited to a thickness greater thanthat for filling the trench 3. The thickness of the substrate oxide film4 formed on the inner surface of the trench 3 is desirably within therange of the order of 0.08 to 0.2 μm. In this example, the substrateoxide film 4 with a thickness of 0.1 μm was formed. The polysiliconlayer 5 is preferably deposited to a thickness above the upper end ofthe masking oxide film 2. In this example, the thickness of thepolysilicon layer 5 was given as 1.2 μm.

Thereafter, an uneven surface of the polysilicon layer 5 is polished byCMP to be a flat face as shown in FIG. 2A with the masking oxide film 2used as a stopper (a polishing termination detecting film). For the CMP,the high purity colloidal silica slurry planerlite-6103 made by FujimiInc. was used with typical polishing conditions of 300 to 600 hP in topring pressure and 50 to 100 rpm in number of table revolution. Since acommon polishing rate of the polysilicon layer 5 is 1 to 2 μm/minute, acommon polishing rate of the oxide film is 10 to 20 nm/minute and thepolishing selectivity ratio of the two is 100 under the conditions, themasking oxide film 2 can be used as a polishing termination detectingfilm. With a known polishing rate and a known film thickness to bepolished, a polishing time can be derived. In this example, themanufacturing steps are carried out under the above conditions. Themanufacturing steps, however, can be carried out without being limitedto the above conditions as far as a flat face as shown in FIG. 2A isobtained.

Next, as shown in FIG. 2B, a gate oxide film 6 is formed by a thermaloxidation method on the surface of the semiconductor substrate in whichthe previously described manufacturing steps have been completed. Thethickness of the gate oxide film 6 is desirably within the range of theorder of 0.05 to 0.15 μm. In this example, the thickness was given as0.1 μm. Thereafter, as shown in FIG. 2C, patterning is carried out toleave the gate oxide film 6 so that the film 6 covers the surfacesection of the polysilicon layer 5 and to remove the oxide films 2 and 6between the trenches, by which the silicon substrate 1 is exposed. Then,as shown in FIG. 2D, on the gate oxide film 6 and the exposed siliconsubstrate 1, an n⁺ doped polysilicon layer 7 is formed, which includesphosphorus with an impurity concentration of 1×10¹⁶ cm⁻³.

In the polysilicon layer 7, as shown in FIG. 3A, an n⁺⁺-source region 9,a p⁺-doped base region (or p⁺-channel region) 8 and an n⁺-buffer region10 are formed. In the method of forming the regions, with a photoresistpatterned in a shape of the n⁺⁺-source region 9 used as a mask, ionimplantation is carried out with boron ions with a dose of 5×10¹⁴ cm⁻³.Moreover, with a photoresist patterned in a shape of the p⁺-channelregion 8 used as a mask, ion implantation is carried out with arsenicions with a dose of 1×10¹⁵cm⁻³. After the photoresists are subjected toashing, driving diffusion is carried out, by which the n⁺⁺-source region9 and the p⁺-channel region 8 are formed. Furthermore, a region, inwhich the n⁺-doped polysilicon layer 7 is left as it is, becomes then⁺-buffer region 10. Subsequently, as shown in FIG. 3B, a BPSG (BoronPhosphoSilicate Glass) film 11 as an interlayer insulator film isdeposited to a thickness of 1 μm, in which a contact hole 11-1 is formedfor an emitter electrode by carrying out patterning and etching.Thereafter, an Al emitter electrode (a cathode electrode) 12 is formed,by which a surface structure on the MOS gate side of the IGBT accordingto the present example is formed (FIG. 3C). The side of the otherprincipal surface (the bottom surface) of the semiconductor substrate 1can be ground as necessary. Moreover, in a p⁺-collector region as ap⁺-anode layer (not shown) formed on the side of the other principalsurface (the bottom surface), an impurity concentration and a thicknesscan be selected as necessary by well-known technology. Further, in thep⁺-collector region, an anode electrode (not shown) is formed so as tobe in an ohmic contact with the p⁺-collector region, by which a verticalIGBT is produced.

Next, the IGBT produced by the above method will be explained. In theembodiment of the IGBT shown in FIG. 3C, applying a voltage positive tothe cathode (emitter) electrode 12, to the gate electrode (the gatepolysilicon layer 5) causes a region of the p⁺-base region 8 near theinterface with the gate oxide film 6 to be inverted into the n-type toform a channel. In this state, a forward bias applied across thecollector (not shown) and the emitter, i.e., across the anode and thecathode, causes electrons to flow into the drift layer (the n⁻ singlecrystal silicon substrate 1) through the channel and an electronaccumulation layer (a region along the gate oxide film 6 in then⁺-buffer region 10) to reach the p⁺-anode layer (not illustrated) onthe bottom surface of the substrate 1. This causes the p-n junctionbetween the p⁺-anode layer and the drift layer to be forward-biased toallow holes to be injected from the p⁺-anode layer to the drift layer.

The injected holes, on arriving at the surface of the drift layer 1,enter the n⁺-buffer region 10. Part of the holes entering the n⁺-bufferregion 10 disappears in the n⁺-buffer region 10 by the recombinationwith electrons. The rest of the holes pass through the n⁺-buffer region10 to be collected into the p⁺-base region 8. The hole current, flowingin the narrow and long polysilicon layer 7 as the layer in which then⁺-buffer region 10 and the p⁺-base region are formed, causes a voltagedrop. Therefore, an n⁺/n⁻ junction formed with the region along the gateoxide film 6 in the n⁺-buffer region 10 as an electron accumulationlayer and the n⁻-drift layer 1 is forward-biased. This allows electronsto be injected into the n⁺-buffer region 10 to enhance the electronconcentration on the cathode side. According to the enhanced electronconcentration, holes with the same concentration are accumulated forsatisfying the charge neutrality condition.

Moreover, the holes, being injected into the n⁺-buffer region 10, alsomake the n⁺/n⁻ junction further forward-biased, by which electrons areinjected into the n⁺-buffer region 10. The polysilicon layer 7 and then-single crystal silicon substrate 1 are separated from each other bythe substrate oxide film 4 in most of their parts except the surface ofa protruded section in the cross section of the drift layer. Therefore,the p-n-p BJT region is a small part of the device and most part is ap-i-n diode region. Moreover, a channel can be formed over the most partof the area of the surface of the substrate to also allow the peripherallength of the channel to be freely increased. However, an excessivelyincreased peripheral length results in excessively high transfercharacteristics of the device that increase a limited current atshort-circuit to lower short-circuit capability. Therefore, this must betaken into consideration in determining the peripheral length.

Next, an explanation will be made about an operation at blocking mode inwhich a forward bias is applied between the collector and the emitterwith a gate potential made equal or negative to an emitter potential. Inthe blocking mode, a depletion layer expands from the p-n junctionformed with the p⁺-base region 8 and the n⁺-buffer region 10. At thesame time, a depletion layer also expands from the gate oxide film 6.This is because the n⁺-buffer region 10 is biased in positive incontrast to the gate electrode whose electric potential is equal to orlower than the emitter potential. The n⁺-buffer region 10, having athickness only equal to the thickness of the polysilicon layer 7, ismade completely depleted by a slight forward bias. With the total amountof the impurity in the n⁺-buffer region 10 prepared at an amount equalto or lower than a certain one, the maximum electric field strength inthe n⁺-buffer region 10 can be restricted.

With the forward bias increased further, the depletion layer extendsinto the n⁻-drift layer. Most of the applied forward bias is held by then-drift layer. This can prevent generation of local peaks in theelectric field strength in the n⁺-buffer region 10 to hardly cause localavalanche breakdowns due to local electric field concentration. Thus, asufficiently high forward breakdown voltage can be ensured. As a result,there is no degradation in the on-voltage to breakdown voltage tradeoffeven though the forward breakdown voltage is increased. This is anexcellent advantage over a related planar or trench IGBT. In the relatedplanar or trench IGBT, it is difficult to avoid local electric fieldconcentrations.

Polysilicon is inferior to single crystal silicon in terms of carriermobility and a carrier lifetime. The carrier mobility and the carrierlifetime in polysilicon, however, are recovered to a large extent byannealing the polysilicon at high temperatures of 1000° C. or above.Technology has been developed to recover mobility while controllingcrystal grain sizes by laser annealing. It is considered that the use ofsuch technology can reduce variations in characteristics such as athreshold value of a gate voltage and transfer characteristics.

In the n⁺⁺-source region 9, in which the n⁺-polysilicon layer 7 is madeto have a high impurity concentration, a significantly high dopingconcentration provides low resistance despite low mobility of carriers,which therefore causes little voltage drop. Moreover, in the aboveexample, since the peripheral length of the p⁺-channel region (thep⁺-base region 8), to which the n⁺-polysilicon layer 7 is changed to bethe p-type, can be comparatively freely determined by pattern design, byincreasing the peripheral length so as to compensate for a voltage dropdue to degradation in mobility, a voltage drop can be brought to thesame degree as that of the related IGBT Furthermore, in the n⁺-bufferregion 10, which is made up of the n⁺-polysilicon layer 7, low mobilityof carriers causes a slight increase in the voltage drop. The voltagedrop, however, makes a small contribution to the total on-voltage.Conversely, a merit can be obtained in which the voltage drop in then⁺-buffer region 10 makes the electric potential of the n⁻-drift layer 1higher to the emitter potential.

The n⁺-electron accumulation layer, made up of a region along the gateoxide film 6 and a region along the substrate oxide film 4 at theprotruded section in the cross section of the n⁻-drift layer 1, asignificantly high electron concentration (around 1×10¹⁹ cm⁻³) and lowelectric resistance cause a small voltage drop. This makes the n⁺/n⁻junction formed with the n⁺-electron accumulation layer and the n⁻-driftlayer 1 further forward-biased, so that electrons are easily injected.Namely, the voltage drop in the n⁺-buffer region 10 makes the carrierdistribution in the n-drift layer in a surface-deviated shape, which isa large characteristic of the invention. This exhibits the advantage ofthe invention that optimizes the on-voltage to turn-on loss tradeoff.This means that the voltage drop in the n⁻-drift layer, occupying mostof the on-voltage share particularly in a high breakdown voltage IGBT,is minimized to a certain turn-off loss.

A short lifetime and low mobility of carriers in the n⁺-buffer region 10shorten the diffusion length of holes as minority carriers to increaserecombination of carriers in the n⁺-buffer region 10. This results in adecrease in the hole current passing through the p⁺-base region 8 andcollected in the emitter electrode 12. Thus, the hole currentcontributing to latchup is made decreased to enhance latchup capability.

Here, a measure can be taken by which the physical properties ofpolysilicon in the polysilicon layer 7 are intentionally made notrecovered. In this case, the diffusion length of the hole in then⁺-buffer region 10 becomes significantly shorter than the length of then⁺-buffer region 10. Thus, most of the holes disappear in the n⁺-bufferregion 10 by the recombination with electrons, so that no hole currentreaches the p⁺-base region 8. Thus enables realization of a latchup-freeIGBT The operation of such an IGBT is essentially different from that ofa related IGBT. In this case, the p⁺-base region 8 is not operated as acollector of a BJT Thus, an equivalent circuit model of a related IGBTis not valid in which a MOSFET and a BJT are combined. An equivalentcircuit of the IGBT such as above is expressed as a circuit in which aMOSFET and a p-i-n diode are combined.

The above structure of the IGBT has a design advantage of requiring noextreme miniaturization of the surface pattern. The cathode (emitter)contact region, as shown in FIG. 3C, is electrically isolated from thedrift layer 1 by the substrate oxide film 4 except that the region isconnected to the drift region 1 only at a section without the substrateoxide film 4, i.e., at the opening in the substrate oxide film 4. Thus,the design dimension of the cathode (emitter) contact region makes nodirect contribution to the characteristics of the drift layer 1. This isin contrast to the related planar or trench IGBT. In the related IGBT,the entire cathode (emitter) region is directly connected to the driftregion, so that its design dimension is directly related to the devicecharacteristics. Therefore, the present example is characterized in thatthe characteristics of the tradeoff are unchanged without particularminiaturization of the n⁺⁺-source region 9.

FIG. 4A to FIG. 6C illustrate cross sectional views each showing aprincipal part of a semiconductor substrate at each of mainmanufacturing steps of another manufacturing method of an IGBT with asurface cathode side high injection structure. As shown in FIG. 4A toFIG. 6C, the manufacturing method in the second example differs from themanufacturing method described in the above example in that the sidewall angle of a trench (an angle formed by the surface of a substrateand the side wall) formed in the step shown in FIG. 4B is smaller than90°. In the second example, the side wall angle of the trench isdesirably between 85 and 90°. By forming such shape, not only is theelectric field concentration reduced at the corner of the bottom of thetrench but also the width of a current path can be widely provided.Therefore, it is more difficult to form an electric field concentration,by which a conduction loss can be further reduced.

Etching conditions for forming a trench with a side wall inclined atsuch an angle were given as: the flow rate of SF₆=40 sccm, the flow rateof HBr=40 sccm, the flow rate of O₂=60 sccm, the pressure=3.3 Pa, theplasma source power=400W, the bias power=40W and the etching time=20sec. Conditions other than that for the bias power are the same as thosefor the manufacturing method of the first example. The side wall angleof the trench can be freely controlled by changing the bias power. Inthe second example, the side wall angle of the trench of 87° wasobtained with the bias power given as 40W. However, the etchingcondition is not limited to the above on condition that the desiredcross sectional shape is obtained. The side wall angle of the trench isdesirably between 85 and 90°.

The polysilicon layer 7 in each of the above examples is explained asbeing made of polycrystalline silicon. The layer 7, however, can be madeof single crystal silicon formed by an epitaxial growth.

FIG. 7A to FIG. 9B schematically illustrate cross sectional views eachshowing a principal part of a semiconductor substrate at each of mainmanufacturing steps of yet another embodiment of an IGBT with a top gatetype surface high injection structure to which lateral epitaxial growthis applied. The top gate type is known as a structure in which a gateelectrode is disposed on the upper side of a gate oxide film and achannel region is formed on the lower side of the gate oxide film.

As shown in FIG. 7A, an n-type FZ-silicon substrate 21 having a mirrorpolished surface is used as a substrate. The resistivity of thesubstrate is preferably within a range of 30 to 200 Ωcm, which isselected depending of the breakdown voltage of the IGBT For example,manufacture by using a substrate with a resistivity of 80 Ωcm allows anIGBT with a breakdown voltage of 1200V to be provided. On the mirrorpolished surface of the substrate 21, an oxide film 22 with a filmthickness of within the range of 0.3 μm to 1 μm is formed by thermaloxidation or CVD growth. Next, as shown in FIG. 7B, with a patternedphotoresist provided on the oxide film 22, the oxide film 22 issubjected to dry etching to be selectively etched in a stripe-like form,by which a large opening 23 is formed. At this time, a cell pitch of 5to 20 μm and the width of 0.5 to 2 μm of the stripe-like oxide film 22are preferable. Here, the cell pitch and the width of the oxide film 22were taken as 10 μm and 1 μm, respectively. Subsequently, as shown inFIG. 7C, a substrate oxide film 24 is formed on the entire surface ofthe substrate 21 by thermal oxidation or CVD growth. Thereafter, anopening 25 is provided at the center of the substrate oxide film 24 byphotolithography. The oxide film 22 and the substrate oxide film 24 areformed in dish-like. The thickness of the oxide film 22, protruding atthe end of the substrate 1 like the edge of the dish, is preferablywithin the range of 0.3 to 1 μm. The thickness of the substrate oxidefilm 24, forming the bottom of the dish, is preferably within the rangeof 0.05 to 0.2 μm. Here, the thickness of the oxide film 22 protrudingat the end and the thickness of the substrate oxide film 24 forming thebottom were taken as 0.5 μm and 0.1 μm, respectively.

Next, as shown in FIG. 7D, with the surface of the silicon substrate 21,exposed by providing the opening 25 in the substrate oxide film 24, usedas a seed layer, an n-silicon epitaxial layer 26 is grown. A typicalprocess gas used for this is a gas in which dichlorosilane ortrichlorosilane is prepared as a main gas, hydrogen gas is prepared as acarrier gas, and arsine or phosphine is added as a doping gas. Areaction pressure is preferably 100 to 760 Torr (1 Torr=133.3 Pa) and asemiconductor substrate (wafer) temperature is preferably on the orderof 1000° C. Here, with phosphine used as a doping gas, the conditionsfor the growth are controlled so that a concentration of phosphorus inthe film becomes 1×10¹⁶ cm⁻³. When the surface of the grown n siliconepitaxial layer 26 becomes higher than the upper surface of thesubstrate oxide film 24, the growth proceeds also in the lateraldirection. Thereafter, when the n-silicon epitaxial layer 26 goes overthe oxide film 22, protruding at the end of the substrate 21, to coverthe entire surface of the substrate 21, the supply of the process gas ismade stopped to terminate the growth of the n-silicon epitaxial layer26.

Next, the wafer 21 is carried into a CMP system to be polished with theoxide film 22 used as a stopper film until the surface of the n-siliconepitaxial layer (single crystal silicon layer) 26 becomes to have a flatcross sectional shape as shown in FIG. 8A. What is important at thistime is to surely stop the polishing by the oxide film 22 taken as areference oxide film (a stopper film) with a polishing selectivity (Sipolishing rate/oxide film polishing rate) increased fifty times or more,preferably one hundred times or more. For this purpose, the high puritycolloidal silica slurry planerlite-6103 made by Fujimi Inc., forexample, is effectively used. Typical polishing conditions were given as300 to 600 hP in top ring pressure and 50 to 100 rpm in number of tablerevolution. The polishing selectivity at this time is about 100 times.The polishing time can be made constant with polishing terminationdetection of some kind effectively carried out for preventinginsufficient polishing (presence of a residue of the epitaxial layerleft higher than the protruded oxide film) or excessive polishing(dishing) from being caused. Conceivable measures taken for this aredetection of motor torque, reflected light measurement and the like.Here, motor torque detection was used for preventing faulty polishing soas to make the thickness of the n silicon epitaxial layer 26approximately constant.

Subsequently, as shown in FIG. 8B, a gate oxide film 27 is formed overthe entire surface by thermal oxidation or CVD. Here, as the gate oxidefilm 27, a thermal oxide film was formed with a thickness of 0.1 μm.Then, as shown in FIG. 8C, a polysilicon layer 28 to be a gate electrodewas formed over the entire surface. Thereafter, as shown in FIG. 8D, thepolysilicon film 28 is partially removed by photolithography. Next, withthe left polysilicon layer 28 used as a mask, ion implantation iscarried out with boron ions with a dose of 5×10¹⁴ cm⁻² and arsenic ionswith a dose of 1×10¹⁵ cm⁻². Then, driving diffusion of implanted ions iscarried out at 1150° C. for two hours in an atmosphere of nitrogen, bywhich a p-channel region (p-base region) 29 and an n⁺⁺-source (emitter)region 30 are formed in the n silicon epitaxial layer 26.

Thereafter, as shown in FIG. 9A, a BPSG film 31 with a thickness ofabout 1 μm is formed over the entire surface to be given as aninterlayer insulator film. Subsequently, an opening 32 is provided forproviding contact. Next, as shown in FIG. 9B, an aluminum electrode (anemitter electrode) 33 with a thickness of 5 μm is formed, by which theIGBT is completed.

The IGBT according to this third example has the following advantages:

-   -   1. The channel region 29 formed with the n-epitaxial layer 26        provides large carrier mobility, by which a resistance loss is        reduced.    -   2. The channel region 29 formed with the epitaxial layer (single        crystal layer) reduces leak current at forward blocking.    -   3. The CMP with the oxide film used as a stopper enables the        epitaxial layer 26 to be a thin film and to be made uniform.        This leads to improvement in breakdown voltage and reduction in        variation in characteristics.

FIG. 10A to FIG. 12 illustrate cross sectional views showing yet anothermanufacturing method of an IGBT with a bottom gate type surface highinjection structure to which lateral epitaxial growth is applied. Thebottom gate type is known as a structure in which a polysilicon gateelectrode is disposed on the lower side of a gate oxide film and achannel region (base region) is formed on the upper side of the gateoxide film. The fourth method differs from the third method in that theIGBT formed has the bottom gate structure and a nitride film is used asa stopper film. A cell pitch is, like in the third example, is desirably5 to 20 μm. In the fourth example, the cell pitch was taken as 10 μm.

In the fourth example, as shown in FIG. 10A, on an n-type FZ-siliconsubstrate 21 similar to that of the third example, a substrate oxidefilm 34 with a thickness of 0.1 μm is formed by thermal oxidation orCVD. On the substrate oxide film 34, as shown in FIG. 10B, a polysiliconlayer 36 is deposited which is patterned to have an opening 35 provided.Then, as shown in FIG. 10C, an oxide film 37 with a film thickness of0.1 μm is formed over the polysilicon layer 36 by thermal oxidation orCVD to be provided as a gate oxide film. The oxide film 37 formed on asection without the polysilicon layer 36 is then removed to partiallyexpose the silicon substrate 21. Next, a nitride film with a filmthickness of 0.5 μm is formed over the entire surface before beingetched into a stripe-like form with a nitride film end 38 being left bythe order of 0.5 to 2 μm as shown in FIG. 10D. Thereafter, as shown inFIG. 11A, with the surface of the exposed silicon substrate 21 used as aseed layer, a silicon epitaxial layer 39 is grown until the entiresurface of the substrate 21 is coated with the n-silicon epitaxial layer39. Then, as shown in FIG. 11B, with the nitride film end 38 used as astopper, planarization of the silicon epitaxial layer 39 is carried out.The nitride film, having selectivity of the same degree as the degree ofthe selectivity of the oxide film, becomes an effective stopper. Forexample, in the case of grinding carried out under the same conditionsas those in the third example with the use of the above-described highpurity colloidal silica slurry planerlite-6103 made by Fujimi Inc.,about one hundred times of selectivity can be obtained even with the useof a nitride film.

Next, with a photoresist patterned in a shape of a p-channel region(p-base region) used as a mask, ion implantation is carried out withboron ions with a dose of 5×10¹⁴ cm⁻³. Moreover, with a photoresistpatterned in a shape of an n⁺⁺-source region 41 used as a mask, ionimplantation is carried out with arsenic ions with a dose of 1×10¹⁵cm⁻³. After the photoresists are subjected to ashing, driving diffusionof implanted ions is carried out at 1150° C. for two hours in anatmosphere of nitrogen, by which the p-channel region (p-base region) 40and the n⁺⁺-source region 41 are formed in the silicon epitaxial layer39 as shown in FIG. 11C. Then, as shown in FIG. 11D, a BPSG film isdeposited on the entire surface to a thickness of 1 μm to be formed asan interlayer insulator film 42 in which a contact hole 43 is formed bypatterning. Next, as shown in FIG. 12, an aluminum electrode (an emitterelectrode) 44 with a thickness of 5 μm is formed, by which a surfacestructure on the MOS gate side of the IGBT is formed. Advantages broughtby the method are the same as those by the method according to the thirdexample.

Furthermore, a manufacturing method can be provided in which themanufacturing methods according to the above examples are mixed. Forexample, a trench like the trench in the first example is formed, inwhich an n-polysilicon layer or an n-epitaxial silicon layer is formedover an insulator film formed on the bottom of the trench. After thesurface of the n-polysilicon layer or the n-epitaxial silicon layer ismade flush with the surface of the protruded section of the substrate,an n⁺⁺-source region, a p-base region (channel region) and an n⁺-bufferregion are formed. Then, a gate insulator film is formed on the surface.Thereafter, a polysilicon gate electrode, an interlayer insulator filmprovided with a contact hole for a source electrode and the sourceelectrode are formed, by which a device can be also provided so that atop gate MOS gate structure is formed. Moreover, a method can beprovided by which, in the above-described trench, a polysilicon gateelectrode with an insulator film put between the bottom of the trenchand the polysilicon gate electrode is formed, a gate insulator film isformed on the surface of the polysilicon gate electrode, and ann-polysilicon layer or an n-epitaxial silicon layer is formed on and incontact with the gate insulator film. After the surface of then-polysilicon layer or the n-epitaxial silicon layer is made flush withthe surface of the protruded section of the substrate, an n⁺⁺-sourceregion, a p-base region (channel region) and an n⁺-buffer region areformed, on which an interlayer insulator film and a source electrode areformed. With such a method, a bottom gate MOS gate structure can be alsoformed.

A semiconductor device and a method of manufacturing the same accordingto the present invention can improve the tradeoff between the on-voltageand the turned-off loss by increasing the amount of electrons injectedfrom a cathode on a surface to increase the amount of carriers on thecathode side in a stable turned-on state of the device for enhancing theIE effect.

While the present invention has been particularly shown and describedwith reference to preferred embodiments thereof, it will be understoodby those skilled in the art that the foregoing and other changes in formand details can be made therein without departing from the spirit andscope of the present invention. All modifications and equivalentsattainable by one versed in the art from the present disclosure withinthe scope and spirit of the present invention are to be included asfurther embodiments of the present invention. The scope of the presentinvention accordingly is to be defined as set forth in the appendedclaims.

This application is based on, and claims priority to, JapaneseApplication Nos. 2005-185877, filed on 27 Jun. 2005, and 2004-256251,filed on 02 Sep. 2004. The disclosures of the priority applications, intheir entirety, including the drawings, claims, and the specificationthereof, are incorporated herein by reference.

1. A semiconductor device having a MOS gate side surface structure,comprising: a semiconductor substrate of one conductivity type; a trenchselectively formed into the semiconductor substrate; a polycrystallinesemiconductor gate electrode region filling the trench; a substrateinsulator film between the trench and the polycrystalline semiconductorgate electrode region; a gate insulator film covering the surface of thepolycrystalline semiconductor gate electrode region; a depositedsemiconductor layer in contact with the gate insulator film in a regionon the trench and in contact with the surface of the semiconductorsubstrate in a region other than the region on the trench, the depositedsemiconductor layer having a buffer region of the one conductivity typein contact with the surface of the semiconductor substrate, a baseregion of the other conductivity type adjacent to the buffer region onthe gate insulator film, and an emitter region of the one conductivitytype adjacent to the base region on the gate insulator film on the sideopposite to the buffer region; an interlayer insulator film covering thebuffer region; and an emitter electrode covering the interlayerinsulator film, and in contact with both the base region and the emitterregion on the side opposite to the side in contact with the gateinsulator film.
 2. The semiconductor device as claimed in claim 1,wherein the buffer region has an impurity concentration higher than thatof the semiconductor substrate.
 3. The semiconductor device as claimedin claim 1, wherein the deposited semiconductor layer is a singlecrystal or polycrystalline semiconductor layer of the one conductivitytype.
 4. The semiconductor device as claimed in claim 1, wherein thetrench has a side wall forming an angle of 90° or less with the surfaceof the semiconductor substrate.
 5. A semiconductor device having a MOSgate side surface structure, comprising: a semiconductor substrate ofone conductivity type; a substrate insulator film selectively formed onthe surface of the semiconductor substrate; a deposited semiconductorlayer formed on the surface of the semiconductor substrate and thesubstrate insulator film, the deposited semiconductor layer having abuffer region of the one conductivity type in contact with the surfaceof the semiconductor substrate, a base region of the other conductivitytype adjacent to the buffer region on the substrate insulator film, andan emitter region of the one conductivity type in the base region, theemitter region being at a position holding the surface of the baseregion between the buffer region and the emitter region; a gateelectrode of polycrystalline semiconductor on the surface of the bufferregion and on the surface of the base region held between the bufferregion and the emitter region; a gate insulator film held between thegate electrode and the buffer region, and between the gate electrode andthe base region; an interlayer insulator film covering the gateelectrode of the polycrystalline semiconductor; and an emitter electrodein contact with both the base region and the emitter region.
 6. Thesemiconductor device as claimed in claim 5, wherein the buffer regionhas an impurity concentration higher than that of the semiconductorsubstrate.
 7. The semiconductor device as claimed in claim 5, whereinthe deposited semiconductor layer is a single crystal or polycrystallinesemiconductor layer of the one conductivity type.